Control for Voltage Regulators

ABSTRACT

A mixed signal approach is applied to detect an output voltage condition as applied to a load. A current mode monitoring approach can be adopted and applied in discrete time using a mixed analog and digital approach. For application to various low drop-out voltage regulator situations, a sensing transistor can be connected in parallel with a feedback loop transistor of the low drop-out voltage regulator circuit to create a sensing current that is proportional to the current passing through the feedback loop transistor and thus the output current provided to the load. This sensing approach can be adapted to sense both overload and light load conditions to allow dynamic power control of the device.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This continuation application claims priority to U.S. application Ser.No. 14/245,293, filed Apr. 4, 2014, which is incorporated herein byreference.

TECHNICAL FIELD

This invention relates generally to controlling provision of voltage tomicrocontrollers, processors, and related peripherals, and morespecifically, to controlling the voltage output from a low drop-outvoltage regulator.

BACKGROUND

Microprocessors or controllers are used in a wide variety ofapplications to control the activities of a variety of devices. Suchelectronic devices require a power supply in order to perform theirfunctions. Depending on the design of a particular device, the voltageapplied may need to be within certain parameters to ensure properfunction of the device receiving the output power. Accordingly, variousmethods are known for controlling an output power that is applied toelectronic devices such as microprocessors, controllers, and theirperipherals.

One particular type of structure that is used to provide a power orvoltage to microcontrollers, controllers, and their peripherals iscalled a low drop-out voltage regulator (LDO). Generally speaking, lowdrop-out voltage regulators monitor an aspect of the power applied to anelectronic device such as a microprocessor or associated peripheral andprovides a feedback that allows control circuitry to maintain the powerwithin certain parameters. An example environment in which a lowdrop-out voltage regulator is applied is illustrated in FIG. 1. Anelectronic device 100 includes powered electronic aspects 105 such as acentral processing unit and associated peripherals that receive powerfrom a battery 110. The battery in this case represents a system voltagethat is available to the electronic device 100, which voltage may comefrom a battery or any other available power source. The LDO 115 operatesin both an analog domain and a digital domain such that the LDO is ableto provide an analog output power to the electronic aspects 105 whilebeing controlled at least in part in the digital domain. For example,the LDO 115 may receive a reference current or voltage from thereference biasing supervision circuit 120, which reference current orvoltage is typically provided in an analog format to the LDO 115.Moreover, the LDO is able to provide a feedback signal that can be usedby a power management circuit 125 that, in turn, can control variouselements of the LDO 115 that operate in a digital domain, whichmodifications to those elements help to control the output power that isprovided to the electronic aspects 105. The clock management circuit 130helps by providing information to the power management circuit 125 tofurther assist in controlling the operating parameters of the LDO 115.

FIG. 2 illustrates one example prior art approach to an LDO 115. In thisillustration, the circuit elements covered by a diagonal arrow are allelements that are controlled in the digital domain, for example, throughreceipt of signals from a power management circuit 125. The circuitelements indicated in box 205 constitute the output stage of the LDOthat provides an output power VCORE, which output power is provided tothe electronic aspects 105. Control circuitry 212 of the LDO 115 uses areference voltage VREF and a feedback voltage VFB to determine how tomodify the digitally controlled elements to regulate the power output atVCORE.

One problem with such prior art low drop-out voltage regulators is theinability to keep up the power management features in the face of asudden drop in applied voltage AVDD. In other words, the power source110 provides an input power AVDD that may vary based on a load appliedto the input power or other aspects of the operating electronic device100. The LDO 115 monitors the effect of those changes and changes thecontrol of the input voltage AVDD to try to maintain the output voltageVCORE within acceptable parameters. The circuitry elements, however,that are used to monitor these power aspects may not be able to reactquickly enough to maintain the output voltage VCORE in the face of asudden drop of the input voltage AVDD. For example, with reference toFIGS. 3 and 4, a typical input voltage AVDD in one application can rangebetween 2.7 and 3.6 volts. The typical output voltage that is applied topower one or more electrical aspects (also called the load) is, in thiscase, a VCORE of about 1.2 volts. Should there be an overloading of theinput power AVDD, the input power received by the low drop-out voltageregulator can drop, for example, from an initial voltage of between 2.7and 3.6 volts to 2.0 volts or less. If that drop in input voltage AVDDoccurs over too short of a timeframe, for example, between 10 and 400microseconds, the circuitry of the low drop-out voltage regulator maynot be able to maintain the output voltage VCORE. As illustrated in FIG.3, in the face of this condition, VCORE may momentarily drop from 1.2volts to 0 volts at point 306. Depending on the electronic aspects beingpowered through the low drop-out voltage regulator, a momentary drop ofpower could result in loss of data or other serious interruptions in theoperation of these so powered electronics.

The cause of such a drop in output voltage VCORE can be furtherunderstood with reference to FIG. 4. More specifically, at the outputstage 405 of the given low drop-out voltage regulator, a drop in theinput voltage AVDD is illustrated by a first arrow 407. This drop involtage, in turn causes the drop in voltage at the gate of a passgatetransistor 410 through which current flows to the output of the lowdrop-out voltage regulator VCORE. The drop in voltage at the passgatetransistor's 410 gate causes a drop in current that passes through thepassgate transistor 410. The drop in current, in turn, causes a drop involtage at the output voltage VCORE that is applied to the load 415. Ifthis series of drops happens too quickly, the loop bandwidth orregulation speed of the low drop-out voltage regulator may simply not beable to keep up. For example, the reaction of the passgate transistor410 and a feedback transistor 456, which provides a feedback signal tothe low drop-out voltage regulators control circuitry, may not occur intime for the control circuitry to modify the operating parameters ofother aspects of the low drop-out voltage regulator to maintain theoutput voltage VCORE at its given value. Moreover, certain low drop-outvoltage regulators that are controlled in part via digital domain havelimited combinations of peripheral and clock combinations that can beapplied to react to such voltage drops.

Accordingly, a variety of modifications to these voltage providers havebeen attempted, each having its own set of drawbacks. In this example ofFIG. 4, a comparator circuit 420 is connected to receive the outputvoltage VCORE from the low drop-out voltage regulator circuit 405. Thecomparator circuit 420 in this case includes a comparator circuitelement 430 that compares the output voltage VCORE to a referencevoltage VREF and outputs corresponding comparison signal indicated asVCORE_OK. This direct voltage monitoring approach can be made veryaccurate; however, this approach consumes an excess amount of additionalcurrent, thereby increasing the overall power usage of the circuit.Also, the addition of a voltage reference element and the comparatorcircuit elements causes an increase in the footprint of the circuitelements in the silicon. Moreover, depending on the voltage range to bemeasured, additional reference voltage or resistor divider circuitryelements must be added, thereby adding additional power consumption.Although this method of detecting the output voltage VCORE is accurate,by operating in a voltage domain, this approach is slower than variouscurrent mode detection approaches consuming the same or less amount ofcurrent.

Another prior art approach to controlling a low drop-out voltageregulator is illustrated in FIG. 5. Here, an example current modemonitoring approach where a sensing circuit 520 is connected to sense acurrent ILOAD that flows through a transistor 522 connected in parallelwith the passgate transistor 510 through which the primary load currentILOAD passes. A current source 524 provides a reference current IREF forcomparison to the current passing through the parallel transistor 522 bya comparator circuit element 530, such as a Schmidt Trigger CircuitElement as known in the art. Unfortunately, this approach illustrated inFIG. 5 suffers from the disadvantage that an overload event can occurthat drops the input voltage AVDD and thus the output voltage VCOREbelow an acceptable level while the measured current stays within avalid range. In other words, the sensing approach can fail in situationswhere the voltage drop occurs too quickly relative to the measuredcurrent, such that this approach may not reliably detect the overloadstate caused by supply drops.

A further prior art approach to monitoring and controlling the outputvoltage from a low drop-out voltage regulator is illustrated in FIG. 6.In this approach, the current mirror circuitry 620 is connected tomonitor current at a variety of points within the output stage 605 ofthe low drop-out voltage regulator circuit. Again, the primary currentsensing is done with relation to the sensing transistor 622 that isconnected in parallel to the passgate transistor 610. Accordingly, thisdesign suffers a similar disadvantage as that of the approach of FIG. 5where an unacceptable delay between the current drop and sensing thecurrent drop can occur. Moreover, most low drop-out voltage regulatorsuse bias current adaptation within the analog domain and done incontinuous time. The resistors and transistors that make up the lowdrop-out voltage regulator circuit are not easily adapted or controlledin the analog domain. Moreover, the dynamic range of sensing the currentis limited to particular ranges and limited node voltage swings.

SUMMARY

Generally speaking, and pursuant to these various embodiments, a mixedsignal approach is applied to detect an output voltage condition asapplied to a load. More specifically, a current mode monitoring approachcan be adopted, that is, applied in discrete time using a mixed analogand digital approach. For application to various low drop-out voltageregulator situations, for example, a sensing transistor can be connectedin parallel with a feedback loop transistor of the low drop-out voltageregulator circuit to create a sensing current that is proportional tothe current passing through the feedback loop transistor, i.e., theoutput current provided to the load. Instead of measuring the outputvoltage directly, or measuring the load current more directly, thisapproach provides a fast sensing implementation because of itsintegration within the low drop-out voltage regulator. The approach isrelatively simple to implement using a limited number of elements, whichin turn provides advantages in using less silicon space and less poweras compared to other approaches to monitoring and controlling a lowdrop-out voltage regulator output. These and other benefits may becomeclearer upon making a thorough review and study of the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The above needs are at least partially met through provision of thecontrol for voltage regulators described in the following detaileddescription, particularly when studied in conjunction with the drawingswherein:

FIG. 1 comprises a block diagram of an example electronic device using alow drop-out voltage regulator as may be configured in accordance withvarious embodiments of the invention;

FIG. 2 comprises a circuit diagram of a prior art of a low drop-outvoltage regulator;

FIG. 3 comprises a graph showing a possible drop in an output voltageVCORE relative to a drop in input voltage AVDD as may occur for somevoltage regulators;

FIG. 4 comprises a circuit diagram of a low voltage drop-out regulatoroutput stage together with a prior art voltage monitoring approach tocontrolling output voltage;

FIG. 5 comprises a circuit diagram of a low drop-out voltage regulatoroutput stage together with a prior art current mode sensor approach forcontrolling output voltage;

FIG. 6 comprises a circuit diagram of a low voltage drop-out regulatoroutput stage together with a prior art current mirror sensing approachfor regulating output voltage;

FIG. 7 comprises a circuit diagram illustrating one example approach formonitoring a low voltage drop-out regulator as configured in accordancewith various embodiments of the invention;

FIG. 8A comprises a graph illustrating potential output voltages withrespect to monitored currents in either an overload or light loadcondition as may be monitored in accordance with various embodiments ofthe invention;

FIG. 8B comprises a graph illustrating potential output currents with aconstant output voltage and with respect to monitored currents in eitheran overload or light load condition as may be monitored in accordancewith various embodiments of the invention;

FIG. 9 comprises a circuit diagram of an example approach to monitoringand controlling a low drop-out voltage regulator circuit as configuredin accordance with various embodiments of the invention;

FIG. 10 comprises a circuit diagram of an example approach to monitoringand controlling a low drop-out voltage regulator circuit as configuredin accordance with various embodiments of the invention; and

FIG. 11 comprises a flow diagram of example approaches to monitoring andcontrolling a low drop-out voltage regulator circuit as configured inaccordance with various embodiments of the invention.

Skilled artisans will appreciate that elements in the figures areillustrated for simplicity and clarity and have not necessarily beendrawn to scale. For example, the dimensions and/or relative positioningof some of the elements in the figures may be exaggerated relative toother elements to help to improve understanding of various embodimentsof the present invention. Also, common but well-understood elements thatare useful or necessary in a commercially feasible embodiment are oftennot depicted in order to facilitate a less obstructed view of thesevarious embodiments. It will further be appreciated that certain actionsand/or steps may be described or depicted in a particular order ofoccurrence while those skilled in the art will understand that suchspecificity with respect to sequence is not actually required. It willalso be understood that the terms and expressions used herein have theordinary technical meaning as is accorded to such terms and expressionsby persons skilled in the technical field as set forth above exceptwhere different specific meanings have otherwise been set forth herein.

DETAILED DESCRIPTION

Referring now to the drawings and, in particular, FIG. 7, an exampleapproach to current mode monitoring of a low drop-out voltage regulatorcircuit in a discrete time and mixed analog/digital approach will bedescribed. In this example, an apparatus for detecting a load and aninput power includes a low drop-out voltage regulator circuit 700configured to provide an output load VCORE to a load 715. The load 715comprises resistive and capacitive elements, which represent how theload 715 is experienced from the point of view of the low drop-outvoltage regulator circuit 700. The output voltage VCORE applied to theload 715 is a result of conditioning an input voltage AVDD that resultsin a current being passed through a passgate transistor 710 of the lowdrop-out voltage regulator circuit 700. This output voltage VCORE isalso connected to pass a current IDS1 through a feedback transistor 716within the low drop-out voltage regulator circuit 700. A current modecomparator circuit 750 is connected to the low drop-out voltageregulator circuit 700 to monitor a low drop-out voltage regulatorcircuit current IDS1 driven by the output voltage VCORE of the lowdrop-out voltage regulator circuit 700. The current mode comparatorcircuit 750 is configured to monitor the low drop-out voltage regulatorcircuit current IDS1 in a discrete time mixed analog/digital approach.FIG. 7 illustrates one particular example of this approach.

In this example, the current mode comparator circuit 750 includes asensing transistor 756 connected in parallel with the feedback looptransistor 716. This sensing transistor 756 is configured to output asensing current IDS7 proportional to the low drop-out voltage regulatorcircuit current IDS1. The current mode comparator circuit 750 furtherincludes a reference current source 760 configured to provide areference current IREF. A comparator circuit 770 is configured toperform a comparison between the sensing current IDS7 and the referencecurrent IREF and to output a comparison signal based on the comparison.In a typical embodiment, the feedback loop transistor 716 is a PMOStransistor having a drain and a source with the source connected toreceive the output voltage VCORE. The low drop-out voltage regulatorcircuit current IDS1 is, in this approach, a current emitted from thedrain of the feedback loop transistor 716. By one approach, thecomparator circuit 770 is a Schmitt-Trigger circuit configured to outputa digital flag signal in response to the sensing current IDS7 droppingbelow the reference current IREF. In other words, the comparator circuit770 compares the sensing current IDS7 to the reference IREF and providesa one-bit signal depending on which of the two currents is higher thanthe other. In FIG. 7, the signal is indicated as the LDO_OVERLOADsignal, which can be provided to a controller element that controls theoperating parameters of the low drop-out voltage regulator circuit 700.So configured, a fast and reliable approach to monitoring the output ofa low voltage drop-out regulator circuit is accomplished throughaddition of only three circuit elements: the sensing transistor 756, thecurrent reference source 760, and the comparator circuit 770. Thus, verylittle area is taken up in the silicon for building the circuit and verylow additional power is taken up by this sensing approach, which can beparticularly advantageous in low power microcontroller applications.

Turning to FIG. 8, a variety of signals and load conditions for the lowdrop-out voltage regulator circuit and sensing approach are illustrated.Here, an output voltage VCORE starts at a maximum level between timesT-0 and T-1. At T-1, the output voltage VCORE begins to drop. The lowdrop-out voltage regulator circuit current IDS1 and sensing current IDS7are proportional to each other and, thus, move in unison as shown in asingle trace in the graph of FIG. 8. In this example, the current IDS1,7 starts at a maximum level at T-0, and at a time T-2 after the outputvoltage VCORE begins to drop at time T-1, the current IDS1, 7 begins todrop. The difference between time T-1 and time T-2 represents the lag insensing the current drop relative to the output voltage VCORE drop. Asthe output voltage VCORE continues to drop, the currents IDS1 and IDS7also drop. The reference current IREF is set to a level IREF min suchthat the sensed IDS7 will cross the reference current IREF min at thepoint of overload represented in the graph of FIG. 8 at time T-4. Inthis approach, an overload is detected prior to the output voltage VCOREreaching a minimum tolerable voltage, which occurs at time T-5 after theoverload condition is sensed at time T-4 by the given sensing approach.Accordingly, although there is a lag between the initial drop in theoutput voltage VCORE and the corresponding drop in the sensed currentIDS7, that lag is not so great so as to miss sensing an overloadcondition prior to the output voltage VCORE is reaching a criticalstage.

Another option for designing such a sensing approach is furtherillustrated in FIG. /8A wherein the sensing approach can be adapted tosense not only an overload condition, but also a light load conditionfor the low drop-out voltage regulator circuit. In this situation, whenthere is a light load on the power source, the output voltage VCORE mayactually be unnecessarily high for the present operating environment. Insuch a situation, the low drop-out voltage regulator circuit andpotentially other elements of the electronic device can be switched to alow power configuration, as long as there is merely a light load towhich output power needs to be provided. In such an approach, thereference current IREF can be switched to a higher IREF MAX levelwherein currents sensed above the IREF MAX level indicate a light loadcondition instead of providing a minimum current IREF MIN used to detectan overload condition. In FIG. 8A, this condition is present during thetimeframe between time T-0 and time T-3. In this light load condition,there is minimum drain or pull on the output voltage VCORE, which inturn, manifests as a current IDS7 being higher than the referencecurrent IREF MAX. The comparator circuit 770 of FIG. 7 in thissituation, can then provide an output signal indicating that the currentIDS7 is higher than the reference current IREF MAX, which signal whenreceived by a controller can allow the controller to change settings forthe low drop-out voltage regulator circuit and other elements to useless power until a time such as T-3 when the sensed current IDS7 dropsbelow the IREF MAX, indicating the end of the light load condition. Inthis manner, the controller receiving a signal from the comparatorcircuit 770 can dynamically adjust the settings of various aspects ofthe circuit to actively manage the power levels of the circuit to reducepower consumption during run-time.

In addition to detecting voltage drops and light load situations, thedescribed approaches may also detect overload current conditions. Asillustrated in FIG. 8B, an output current provided to a load ILOAD canfluctuate without appreciable change in the output voltage VCORE. Here,the load current ILOAD starts rising at a time T-11. Because of thecircuit design described herein, the low drop-out voltage regulatorcircuit current IDS1 and sensing current IDS7 will vary inversely withthe load current ILOAD when the output voltage VCORE is constant,accordingly starting to drop at T-11. At time T-12 the sensing currentcrosses a threshold current IREF MAX thereby indicating that the circuithas passed from a light current load condition to a normal current loadcondition, which condition shift is sensed by the current modecomparator circuit. As the load current ILOAD continues to rise with aconstant output voltage VCORE, the sensing current IDS7 continues todrop until it crosses at time T-13 a further threshold IREF MIN therebyindicating to the current mode comparator circuit that the circuit haspassed from a normal current state to an overload current state.

FIG. 9 illustrates one approach to implementing such dynamic controlover an electronic device. In this example, the current mode comparatorcircuit 950 that is connected to sense current from the low drop-outvoltage circuit output stage 700 includes an N-bit digital to analogconversion circuit 965 configured to control the reference currentsource 960 to output a high reference current. In this approach, thecomparator circuit 970 is configured to output a digital flag signal inresponse to sensing current exceeding the high reference current. Thus,a controller connected to control the elements including the referencecurrent source 960 and the comparator circuit 970 can actively monitorand control power usage of the electronic device in a manner similar tothat described above with respect to FIG. 8.

Still another example of monitoring and controlling a voltage providercircuit is illustrated in FIG. 10. In this approach, the current modecomparator circuit 1050 includes a sensing transistor 1056 connected andparallel with the feedback loop transistor 716, and configured to outputa sensing current IDS7 proportional to the low drop-out voltageregulator circuit current passing through the feedback loop transistor716. A resistive element 1060 is connected to have the sensing currentIDS7 pass through the resistive element 1060 to provide a sensingvoltage VR that is proportional to the sensing current IDS7. In thisapproach, instead of using a current based comparator circuit, an N-bitanalog to digital comparator circuit 1065 is connected to convert thesensing voltage VR to a digital output. The digital output can have asmany bits as needed to provide sufficient information regarding theoutput load of the low drop-out voltage regulator circuit 700. Thisinformation is received by a controller device 1070. The controllerdevice 1070 is configured to receive the digital output and control thelow drop-out voltage regulator circuit 700 to operate at a low powersetting in response to the digital output's indicating the sensingcurrent IDS7 is exceeding a high current threshold. Similarly, thecontroller device 1070 can control the low drop-out voltage regulatorcircuit to operate in a higher power setting in response to the digitaloutput's indicating the sensing current IDS7 is dropping below a givenlow current threshold, such as in an overload situation.

So configured, the basic approach of using a discrete time mixedanalog/digital approach can be modified readily to expand theresponsiveness of controlling a power voltage provider such as a lowdrop-out voltage regulator. These approaches are fast and highlyadaptive to a given situation. Moreover, these approaches generallyconsume less power and less silicon space as compared to otherapproaches given the limited number of elements needed to be added tothe low drop-out voltage regulator circuit to monitor its performance.

Example methods of operation for such power provision circuits will bedescribed with reference to FIG. 11. By one approach, a method fordetecting the load experienced by a power provider includes a lowdrop-out voltage regulator circuit providing 1110 an output voltage to aload. A low drop-out voltage regulator circuit current driven by theoutput voltage of the low drop-out voltage regulator circuit ismonitored 1120 in a discrete time mixed analog/digital approach with acurrent load comparator circuit. The low drop-out voltage regulatorcircuit current driven by the output voltage is passed 1130 through afeedback loop transistor of the low drop-out voltage regulator circuit.In one example, the feedback loop transistor is a PMOS transistor havinga drain and a source with the source connected to receive the outputvoltage. In this case, the method includes emitting the low drop-outvoltage regulator circuit current from the drain of the feedback looptransistor. A sensing current proportional to the low drop-out voltageregulator circuit current is output 1140 from a sensing transistor ofthe current load of comparator circuit. The sensing transistor isconnected in parallel with the feedback loop transistor. The sensing ofthe sensing current can be accomplished and fed back to a controller ina variety of ways. By one approach, a comparator circuit compares 1152the sensing current to a reference current. The comparator circuit thenoutputs 1154 a comparison signal based on the comparison of the sensingcurrent and the reference current. Where the output comparison signal ismerely a 1-bit flag, the comparator circuit may be a Schmitt-Triggercircuit outputting a digital flag signal in response to the sensingcurrent dropping below the reference current. The reference current canbe set 1156 based on the desired operating parameters of the givencircuit. By one approach, the reference current may be set 1156 byhaving an N-bit digital to analog conversion circuit of the comparatorcircuit control the reference current to be either a high referencecurrent or a low reference current, depending on the circuit statedesired to be monitored. The comparator circuit in this case outputs adigital flag signal in response to the sensing current exceeding thehigh reference current or dropping below a low reference current.

By another approach illustrated on the right hand side of FIG. 11, anN-bit analog to digital comparator circuit converts 1162 a sensingvoltage derived from the sensing current to a digital output. The methodmay further include a controller device receiving the digital output andcontrolling 1164 the low drop-out voltage regulator circuit to operate,for example, in a low power setting in response to the digital output'sindicating that the sensing current is exceeding a high currentthreshold. Similarly, the controller device may control the low drop-outvoltage regulator circuit to operate in a high power setting in responseto the digital output's indicating that the sensing current drops belowa low current threshold, such as in an overload situation.

So configured, the proposed approaches can monitor a relevant lowdrop-out voltage regulator circuit operating point other than the outputvoltage to sense more quickly potential failures in provision ofadequate output voltage. The circuit is simple and robust to implement,and typically only a small fraction of bias current is needed to effectthe comparison. The silicon area overhead is small compared to otherapproaches to monitoring the low drop-out voltage regulator outputvoltage, and in certain applications, the quiescent current overhead canbe made very small. In one application, the current overhead forimplementing such a solution was about 10 nanoamps whereas a reasonablyfast output comparator used in various prior approaches can consume upto or around 100 nanoamps depending on its speed. Moreover, in contrastto certain control schemes that require several look-up tables that lackflexibility and power efficiency, various proposed approaches can reacton the actual low drop-out voltage regulator circuit loading situationas opposed to acting in a predictive state. Thus, more power istypically consumed in calculating the predictive state as opposed tosimply monitoring the current state of the device as described.

Those skilled in the art will recognize that a wide variety ofmodifications, alterations, and combinations can be made with respect tothe above described embodiments without departing from the scope of theinvention. Such modifications, alterations, and combinations are to beviewed as being within the ambient of the inventive concept.

What is claimed is:
 1. An apparatus for detecting load on an inputpower, the apparatus comprising: a low dropout voltage regulator circuitconfigured to provide an output voltage to a load; a current modecomparator circuit connected to the low dropout voltage regulatorcircuit to monitor a low dropout voltage regulator circuit currentdriven by the output voltage of the low dropout voltage regulatorcircuit; wherein the current mode comparator circuit is configured tomonitor the low dropout voltage regulator circuit current in a discretetime mixed analog/digital approach.
 2. The apparatus of claim 1 whereinthe low dropout voltage regulator circuit comprises a feedback looptransistor connected to pass the low dropout voltage regulator circuitcurrent driven by the output voltage; and wherein the current modecomparator circuit comprises: a sensing transistor connected in parallelwith the feedback loop transistor and configured to output a sensingcurrent proportional to the low dropout voltage regulator circuitcurrent; a reference current source configured to provide a referencecurrent; a comparator circuit configured to perform a comparison betweenthe sensing current and the reference current and to output a comparisonsignal based on the comparison.
 3. The apparatus of claim 2 wherein thecomparator circuit comprises a Schmitt-Trigger circuit configured tooutput a digital flag signal in response to the sensing current droppingbelow the reference current.
 4. The apparatus of claim 1 wherein the lowdropout voltage regulator circuit comprises a feedback loop transistorconnected to pass the low dropout voltage regulator circuit currentdriven by the output voltage; and wherein the current mode comparatorcircuit comprises: a sensing transistor connected in parallel with thefeedback loop transistor and configured to output a sensing currentproportional to the low dropout voltage regulator circuit current; aresistive element connected to have the sensing current pass through theresistive element to provide a sensing voltage proportional to thesensing current; an n-bit analog to digital comparator circuit connectedto convert the sensing voltage to a digital output.
 5. A method ofdetecting load on a microcontroller, the method comprising: a lowdropout voltage regulator circuit providing an output voltage to a load;monitoring a low dropout voltage regulator circuit current driven by theoutput voltage of the low dropout voltage regulator circuit in adiscrete time mixed analog/digital approach with a current modecomparator circuit.
 6. The method of claim 5 further comprising: passingthe low dropout voltage regulator circuit current driven by the outputvoltage through a feedback loop transistor of the low dropout voltageregulator circuit; and outputting a sensing current proportional to thelow dropout voltage regulator circuit current from a sensing transistorof the current mode comparator circuit, the sensing transistor connectedin parallel with the feedback loop transistor; a comparator circuitcomparing the sensing current and a reference current; the comparatorcircuit outputting a comparison signal based on the comparison of thesensing current and the reference current.
 7. The method of claim 6further comprising a Schmitt-Trigger circuit of the comparator circuitoutputting a digital flag signal in response to the sensing currentdropping below the reference current.
 8. The method of claim 5 furthercomprising: passing the low dropout voltage regulator circuit currentdriven by the output voltage through a feedback loop transistor; andoutputting a sensing current proportional to the low dropout voltageregulator circuit current from a sensing transistor connected inparallel with the feedback loop transistor; an n-bit analog to digitalcomparator circuit converting a sensing voltage derived from the sensingcurrent to a digital output.